Selasi Etchey EE Project Portfolio

C2MOS Frequency Divider (Divide-by-2)

Circuit Description: 

A C2MOS latch is a type of dynamic latch that stores its state on the present device capacitances rather than with back-to-back amplifying stages that enforce a latched state (as is the case with static latches). The C2MOS latch acts as an inverter when sensing the input data on a clocked edge, and when the clock changes polarity, the state of the latch is stored due to capacitance on the output node. Since each latch inverts, it is possible to build a frequency divider out of the C2MOS latch topology in a similar method that can be seen in establishing negative feedback in Ring Oscillators (this divider topology can be approximated as a Ring Oscillator that is dependent on its input clock frequency). Each C2MOS holds the state of it’s last value until the next input transition, and thus the output frequency is half the frequency of the input clock with 2 latches present. The following inverter is needed to provide negative feedback in the loop, and the final inverter stage acts as an isolation buffer. 

Figure 1: Divide-by-2 Circuit Cadence Schematic

Component	W/L
M1	2 / 0.15
M2	1 / 0.15
M3	0.5 / 0.15
M4	1 / 0.15
M5	2 / 0.15
M6	1 / 0.15
M7	0.5 / 0.15
M8	1 / 0.15
M9	0.84 / 0.15
M10	0.84 / 0.15
M11	0.84 / 0.15
M12	0.84 / 0.15

 Table 1: Device Sizing Table

• Clocked FETs had width constraints and all FETs have length constraints. Layout process was simplified by including the non-clocked latch FETs on the same fingered devices by making them the same width as the clocked FETs.
• Output Buffer and Inverter were sized to minimum widths to maximize output frequency (minimizing capacitive loading)

Figure 2: Divide-by-2 Circuit Layout

Figure 3: Pre- Extraction/Layout Divide-by-2 Circuit Waveforms and Simulation Metrics

In Figure 3 we can see the waveforms of the divider pre-layout and parasitic extraction. The maximum input frequency of the divider is 9.434GHz which results in an average power dissipation of 202.3uW

Figure 4: Post- Extraction/Layout Divide-by-2 Circuit Waveforms and Simulation Metrics

In Figure 4 we can see the waveforms of the divider after layout and parasitic extraction. The maximum input frequency of the divider is about 33% less than pre-layout, sitting at 6.211GHz, and average power dissipation is slightly less than in the pre-layout case, sitting at 199.9uW.